In general, regarding a patterning structure implemented on a substrate for installing an IC chip, the degree of freedom thereof is low and the structure thereof is complicated. Especially, in an optical module that performs photoelectric conversion, the above tendency becomes apparent in the case that the number of optical elements on a substrate is large.
For example, as described in Patent-related Document 1, in the case of a prior-art optical module, optical elements such as a semiconductor laser, a photodiode, or the like that performs photoelectric conversion is included as a package within the optical module, and a part of the package comprises a ceramic substrate. The ceramic substrate comprises a multilayer structure; and conductor patterns and ground conductors, through which signals propagate, are patterned within the substrate or on the surface of the substrate in such a manner that the conductor patterns and the ground conductors do not cross each other.
A general factor that makes the patterning structure complicated is that a pattern for high-speed signals and a pattern for ground are placed in proximity to each other in an optical module. In an example of an optical module in Patent-related Document 1 (FIG. 1 of Patent-related Document 1), two lead pins for high-speed signals are arranged in proximity to each other, and lead pins for ground are arranged beside the pair of the two lead pins. Specifically, in FIG. 1 of Patent-related Document 1, a signal input/output part that is used for transmission of differential signals and has a GSSG (GND-SIGNAL-SIGNAL-GND) structure is shown, and it is to be connected to a conductor pad or a ground pad through vias within a multilayer substrate.
Also, there is another recent example of a prior-art optical module, wherein a silicon photonics technique is used for integrating and arranging a driver IC on a silicon-photonics chip, for the purposes of downsizing of a chip and reduction of electric power consumption (Non-patent-related Document 1). In the case of this example, since respective optical elements such as a semiconductor laser and so on are also installed on the silicon-photonics chip, increasing of the number of parts is inevitable. In other words, it is necessary to take into consideration, when designing a pad array region for connecting with the IC on a silicon-photonics chip, the matters such that (i) the degree of freedom is very low, and (ii) crossing of electric wires has to be avoided.
Generally, in a prior-art optical module such as that described in Non-patent-related Document 1, pads formed on a substrate and pads for connecting with the IC are connected by use of a multilayered wiring structure, for dealing with the matters described above. However, in the case that a multilayered wiring structure such as that described above is adopted, the structure becomes complicated and, further, wiring resistance becomes very large since it is necessary to built wiring between respective layers through vias.